A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication

AND ITS IMPLEMENTATION IN FPGA COPROCESSOR FOR SECURED ETHERNET COMMUNICATION Rourab Paul, Sangeet Saha, J K M Sadique Uz Zaman, Suman Das, Amlan Chakrabarti and Ranjan Ghosh Email :{rourabpaul, sangeet.saha87, jkmsadique, aami.suman}@gmail.com, [email protected], [email protected] A.K.Choudhury School of Information Technology , Dept. of Computer Science and Engineering and Institute of Radio Physics and Electronics, University of Calcutta, 92 A. P. C. Road, Kolkata – 700 009, India Abstract In the field of cryptography till date the 1-byte in 1-clock is the best known RC4 hardware design [1], while the 1-byte in 3clocks is the best known implementation [2,3]. The design algorithm in [1] considers two consecutive bytes together and processes them in 2 clocks. The design of 1-byte in 3-clocks is too much modular and clock hungry. In this paper considering the RC4 algorithm, as it is, a simpler RC4 hardware design providing higher throughput is proposed in which 1-byte is processed in 1-clock. In the design two sequential tasks are executed as two independent events during rising and falling edges of the same clock and the swapping is directly executed using a MUX-DEMUX combination. The power consumed in behavioral and structural designs of RC4 are estimated and a power optimization technique is proposed. The NIST statistical test suite is run on RC4 key streams in order to know its randomness property. The encryption and decryption designs are respectively embedded on two FPGA boards with RC4 in a custom coprocessor followed by Ethernet communication.